Senior ASIC Verification Engineer - PMU
Core
Architecting next-generation PMU (Power Management Unit) IP for AI datacenter chips, focusing on power efficiency optimization across idle and active scenarios.
Role type
Senior ASIC Verification Engineer (PMU)
Builds
PMU IP with RISC-V core and custom control logic for NVIDIA datacenter products
Domain
Semiconductor / ASIC Design / Power Management
Deliverable
production ML models | product features
Required skills
RTL design, frontend ASIC design, micro-architecture implementation, silicon debug, power architecture collaboration
Preferred skills
active power/low power design, system-level control features
Technologies
RISC-V, RTL
Responsibilities
Define architecture/micro-architecture for power features, support silicon debug, implement micro-architecture to RTL design
Seniority
Senior, hands-on IC
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