Principal Engineer PD
Core
Senior Physical Design Engineer developing next-generation transceiver IPs for high-speed connectivity in advanced technology nodes.
Role type
Senior IC physical design engineer (transceiver/PHY)
Builds
High-speed transceiver IPs and chiplet-based SoC designs
Domain
Semiconductor hardware design, high-speed interconnects
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Floorplanning, placement, CTS, routing, IR drop mitigation, DRC/LVS/ANT/ERC signoff, timing closure, high-speed IP integration, scripting automation
Preferred skills
Advanced technology node experience, high-frequency datapath/DSP design, hierarchical design, physical-aware synthesis
Technologies
ICC2, Innovus, Voltus, RedHawk, Calibre, Tcl, Python, Perl
Responsibilities
Perform block-level and top-level physical implementation including floorplanning, placement, CTS, routing, and physical verification; Collaborate with RTL and STA teams for timing, area, and power convergence; Optimize EM/IR, congestion, clock skew, and RC extraction; Integrate IPs with attention to physical interfaces and timing alignment; Support floorplan development, ECO implementation, and tapeout signoff; Ensure clean verification databases using industry-standard tools; Develop automation scripts to improve physical design flows.
Seniority
Senior, hands-on IC