Senior SOC Clocks RTL Design Engineer
Core
Technical lead for clocking logic development on next-generation networking System-On-Chip (SOC), responsible for PLL integration, clock generation, distribution, and domain crossing.
Role type
Senior IC RTL Design Engineer (Clocks)
Builds
Clocking infrastructure for high-performance networking SoCs
Domain
Semiconductor / Networking SoC Design
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/SystemVerilog), clocking architecture, PLL integration, clock tree synthesis, static timing analysis (STA), formal verification, CDC/RDC analysis, design for test (DFT), low-power design (DVFS, clock gating)
Preferred skills
SOC-level clocking experience, high-speed interconnect design, automation for RTL integration
Technologies
Verilog, SystemVerilog, SDC, UPF
Responsibilities
Lead clocking logic implementation from spec to tape-out, mentor RTL engineers, collaborate with Physical Design on timing convergence, partner with Verification on testplan and debug, support Software teams on clock programming sequences
Seniority
Senior, hands-on IC
