SOC Clocks RTL Design Engineer
Core
Own the SOC clocking logic end-to-end for next-generation networking chips, translating micro-architecture specs into synthesizable RTL and driving designs to silicon.
Role type
Senior IC RTL Design Engineer (Clocking)
Builds
SOC clock generation, distribution, control logic, and clock domain crossing infrastructure for networking chips.
Domain
Semiconductor / SoC Design / Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog/SystemVerilog RTL design, clock generation and distribution, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, clock domain crossing (CDC), synthesis awareness, timing analysis, linting, formal verification, physical design collaboration
Preferred skills
PLL/clock generator integration, clock tree constraint development, SOC-level clocking architecture ownership, automation flow development for RTL integration
Technologies
Verilog, SystemVerilog
Responsibilities
Write synthesizable RTL for clock logic from spec to tape-out; define SOC clock and reset architecture with micro-architecture team; own CDC closure; partner with backend teams on clock tree implementation and timing convergence; support software teams on clock programming and low-power flows; drive design quality via lint, CDC/RDC, and formal checks; develop automation flows for scalable design checking; support post-silicon bring-up.
Seniority
Senior, hands-on IC
