ASIC TOP Floorplan Design Engineer
Core
Design and optimize floorplans for next-generation GPUs and SoCs, influencing early design decisions to solve timing, routing congestion, and area issues.
Role type
Senior IC ASIC Top Floorplan Design Engineer
Builds
High-performance GPUs and System-on-Chips (SoCs) for AI, autonomous driving, and consumer graphics
Domain
Semiconductor / ASIC Physical Design / AI Hardware
Deliverable
production ML models | product features
Required skills
ASIC floorplan design, timing closure, power/clock distribution, packaging, P&R, Verilog/System Verilog, Python, C/C++, AI tool development
Preferred skills
Large-scale ASIC floorplan development, building projects from ground up using AI tools
Technologies
Verilog, System Verilog, Python, Perl, C/C++, Cursor, GitHub Copilot, Windchill
Responsibilities
Develop and optimize floorplans during early chip development; drive area review processes; collaborate with design teams to identify area and interconnect improvements; solve timing and routing congestion issues; build tools and improve infrastructure using AI to optimize chip area and execution speed
Seniority
Mid-level to Senior, hands-on IC
