MTS, AI Optimized Memory Digital Design Engineer
Core
Design and implement high-performance, silicon-proven memory architectures for AI workloads, translating architectural vision into efficient hardware.
Role type
Senior IC digital design engineer (AI memory architecture)
Builds
Next-generation memory systems for AI platforms and applications
Domain
Semiconductor / AI Hardware / Memory Systems
Deliverable
production ML models | product features
Required skills
Digital design, microarchitecture development, SystemVerilog RTL, synthesis flows, PPA optimization, computer architecture, memory systems, SoC-level behaviors, C/C++/Python programming
Preferred skills
Memory interfaces, reliability features, media management, RTL implementation cost analysis, Agentic AI tools
Technologies
SystemVerilog, C, C++, Python
Responsibilities
Translate architecture requirements into scalable microarchitectures; Design and review SystemVerilog RTL for memory systems; Perform synthesis and early PPA analysis; Develop microarchitecture documentation; Evaluate architectural and implementation tradeoffs
Seniority
Senior, hands-on IC