Senior Silicon Engineer
Core
Own block-level DFT architecture, specifications, and implementation for logic and memory test solutions, driving timing closure and signoff across Scan, MBIST, LBIST, IJTAG, and in-system test modes.
Role type
Senior IC silicon engineer (DFT & STA)
Builds
High-quality silicon with robust DFT infrastructure including test clocks, OCCs, clock muxing, and clock-gating architecture.
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (DFT infrastructure, test solutions)
Required skills
DFT architecture design, Static Timing Analysis (STA), ATPG (Scan, Stuck-At, At-Speed), Memory BIST, JTAG, timing closure, SDC generation, Tcl/Perl scripting, EDA tool usage (Siemens Tessent, Synopsys TestMax, Genus, Fusion Compiler), multi-clock/low-power design analysis, post-silicon debug correlation
Preferred skills
AI-assisted workflow development, automation of DFT flows, experience with large SOCs and IP blocks (PLLs, IOs, Power circuits)
Technologies
Siemens Tessent, Synopsys TestMax, Genus, Fusion Compiler, Primetime, Tcl, Perl
Responsibilities
Develop and maintain DFT STA constraints, timing exceptions, and signoff methodologies; Analyze and resolve DFT timing issues in complex multi-clock and low-power designs; Develop automation and AI-assisted workflows to improve DFT timing analysis efficiency; Support post-silicon debug by correlating timing analysis with silicon test results; Collaborate across Architecture, Design, Verification, Physical Design, CAD, Manufacturing, and Post-Silicon teams
Seniority
Senior, hands-on IC
