Physical Design Engineer
Core
Backend implementation engineer responsible for floorplanning, placement, CTS, routing, timing closure, and physical signoff for ASIC chips.
Role type
Physical Design Engineer (Backend Implementation)
Builds
ASIC chips (Trusted Control/Compute Units) for AI-powered digital infrastructure
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, Timing Closure, ECO Implementation, Physical Verification (DRC/LVS/ERC), Tcl scripting, Timing Analysis (Setup/Hold), Power Optimization
Preferred skills
Python scripting, Leakage reduction, Low-power design techniques, Flow automation
Technologies
Cadence Innovus, Synopsys ICC2, PrimeTime, Tempus, Calibre, ICV
Responsibilities
Perform block-level and subsystem-level implementation from netlist to GDS; Analyze and resolve timing, congestion, and routing issues; Debug timing violations and implement solutions; Support DRC, LVS, ERC, and density closure activities; Develop Tcl/Python scripts to automate flow tasks; Collaborate with RTL, DFT, and DV teams.
Seniority
Mid-level, hands-on IC