Staff Engineer, Physical Design
Core
Physical design and methodology for next-generation high-performance processor chips in leading-edge CMOS processes for server, 5G/6G, and networking applications.
Role type
Staff Engineer, Physical Design
Builds
Custom Processor/ASIC solutions and data infrastructure IP
Domain
Semiconductor / Chip Design / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Block-level PNR, Synthesis, Place and Route, Timing analysis and closure, Timing and logic ECOs, Scripting (Tcl, Perl, Makefile), Static timing analysis, EM/IR-Drop/Crosstalk analysis
Preferred skills
Physical verification, Formal verification
Technologies
Cadence Genus, Cadence Innovus, Synopsys IC Compiler, Synopsys Fusion Compiler, Tempus, PrimeTime, Voltus, PrimeRail, Calibre, LEC, Formality
Responsibilities
Maintain and enhance Place and Route Flow, Perform synthesis, place and route, and timing analysis/closure on complex logic blocks, Develop and implement timing and logic ECOs, Debug and resolve block-level timing issues at the partition level
Seniority
Staff, hands-on IC
