Senior Principal ASIC Design Engineer
Core
Senior technical leader driving ASIC design for next-generation Ethernet and Scale-Up (ESUN) connectivity products for rack-scale AI infrastructure.
Role type
Senior Principal ASIC Design Engineer (Technical Lead)
Builds
High-performance Ethernet controllers, MACs, NIC datapaths, packet processing pipelines, and AI interconnect fabrics
Domain
Semiconductor / High-speed Networking / AI Infrastructure
Deliverable
production ML models | product features
Required skills
ASIC/SoC design, RTL design, microarchitecture, high-speed Ethernet controllers, MAC design, NIC architectures, packet processing engines, RDMA architectures, RoCE, InfiniBand concepts, high-speed interconnects (Ethernet, PCIe), AI scale-up fabrics, complete ASIC development flow, technical leadership
Preferred skills
UALink, UCIe, PCIe Gen 6/7, advanced Ethernet architectures, SmartNICs, DPUs, switch datapaths, Ethernet-based scale-up networking for AI/HPC, leading architecture for advanced-node ASIC tapeouts
Technologies
UALink, UCIe, PCIe Gen 6/7, Ethernet, RoCE, InfiniBand
Responsibilities
Define and drive ASIC architecture for Ethernet/ESUN connectivity products; Lead architecture and microarchitecture for high-performance Ethernet controllers and NIC datapaths; Design packet processing architectures, DMA engines, and queue management; Drive execution from architecture through RTL, integration, verification, tapeout, and post-silicon bring-up; Serve as a technical authority across digital, networking, and system domains
Seniority
Senior Principal, hands-on IC with technical leadership
