Senior Logic Design Engineer
Core
Design and build PCIe subsystems and other IP blocks for System-on-Chip (SoC) implementations, ensuring they meet area, power, and performance requirements.
Role type
Senior IC logic design engineer (SoC/PCIe)
Builds
PCIe subsystems and custom IP blocks for SoCs
Domain
Semiconductor / Digital Logic Design
Required skills
PCIe protocol design, AXI/APB interface protocols, ARM Fabric IP, IPXACT, Python/Tcl/Perl scripting, EDA tools (VCS, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus), UPF low power intent, clock crossing techniques, Static Timing Analysis (STA), SDC commands, timing constraints
Preferred skills
Micro-architectural knowledge, design quality checks (Synthesis, Lint, CDC, RDC, Logic Equivalence), low power design principles, timing signoff fundamentals
Responsibilities
Build PCIe subsystems composed of multiple IP, collaborate with architecture and IP providers, assess and refine implementation for area/power/performance, perform design quality checks, understand dataflow and clocking requirements, automate tasks using scripting, deliver high-quality functional blocks on schedule
Seniority
Senior, hands-on IC
