Staff Engineer, ASIC Digital Design
Core
Design next-generation DRAM/NAND/SSD controllers and systems, translating architectural requirements into detailed microarchitecture specifications and robust hardware implementations.
Role type
Staff IC ASIC Digital Design Engineer
Builds
High-speed ASICs and memory controller IP for Micron's product portfolio
Domain
Semiconductor / Memory and Storage
Required skills
SystemVerilog, RTL design, ASIC development flow, high-speed IO crossings, analog/mixed-signal circuits (CMOS/CML, PLL, DLL, CDR), DRAM interfaces, memory-system RAS, synthesis, linting, equivalency, formal verification, Linux shell scripting, Python
Preferred skills
Generative AI in ASIC design flow, AI tools in ASIC design flow
Technologies
SystemVerilog, Synopsys/Cadence (implied by synthesis/verification context), Linux, Python
Responsibilities
Translate architectural requirements into microarchitecture specifications; Lead development of digital designs interacting with analog designs and 3rd party IP; Design and develop RTL for controllers; Own RTL development, simulation, synthesis, timing closure, formal verification, and gate-level validation; Partner with Design Verification, Analog Design, Synthesis, and Physical Design teams; Provide technical leadership through design reviews and mentoring; Support chip bring-up and lab validation.
Seniority
Staff, hands-on IC with leadership
