Senior Principal Engineer, Physical Designer
Core
Senior leader shaping long-term vision and leading RTL-to-GDSII implementation for next-generation high-performance processor chips in leading-edge CMOS processes for server and networking applications.
Role type
Senior Principal Engineer, Physical Designer (Strategy & Leadership)
Builds
Next-generation high-performance SoCs for server and networking applications
Domain
Semiconductor / Custom Processor/ASIC / Physical Design
Required skills
Hierarchical physical design strategies, ASIC design flow, RTL integration, synthesis, timing closure, EDA tools, automation scripting (Makefile, Tcl, Python, Perl), team leadership, cross-functional collaboration
Preferred skills
EM/IR-Drop/crosstalk analysis, formal or physical verification, AI/ML-driven optimization in physical design tools
Technologies
PrimeTime, Tempus, PTSI, Voltus, Redhawk, PrimeRail, Quantus, StarRC, Formality, Verplex, Calibre, Hercules
Responsibilities
Shape long-term vision for physical design capabilities and infrastructure, Lead RTL-to-GDSII implementation for multiple SoC programs, Provide strategic leadership and technical direction to physical design teams, Mentor and develop engineering talent, Oversee team structure, hiring, performance management, and career development, Drive cross-functional collaboration with design teams, Drive development and adoption of next-generation physical design methodologies, flows, and automation
Seniority
Principal, strategy & mentorship
