SoC Clocking Specialist (Physical Design)
Core
Lead clock architecture and physical implementation for next-generation edge AI hardware SoCs.
Role type
Senior IC physical design engineer (clocking)
Builds
High-performance, power-efficient clock trees and networks for edge AI silicon
Domain
Semiconductor / VLSI / Edge AI
Deliverable
production ML models
Required skills
Clock Tree Synthesis (CTS), SPICE simulation, Static Timing Analysis (STA), IP integration (PLL/DLL), Python/Tcl scripting, cross-functional collaboration
Preferred skills
Advanced process node expertise, variation modeling, mesh/hybrid topology design
Technologies
Synopsys ICC2/PrimeTime, Cadence Innovus/Tempus, HSPICE, CustomSim
Responsibilities
Define clock gating strategies and synchronous/asynchronous boundaries; own end-to-end CTS strategy to drive timing closure; run SPICE simulations on critical clock paths; architect custom clock distribution networks; integrate high-speed clocking IPs; establish CTS and SPICE analysis methodologies
Seniority
Senior, hands-on IC
