Physical ASIC Design Implementation Engineer
Core
Physical Implementation engineer for full backend (P&R) projects from netlist-in to GDSII-out flow, handling toplevel chips and blocklevel blocks.
Role type
Senior IC physical design implementation engineer
Builds
GDSII outputs for toplevel chips and blocks
Domain
Semiconductor / ASIC Physical Design
Required skills
Cadence Innovus Place & Route flow, Floorplanning, Power grid design, Place/CTS/Routing, Timing closure (setup/hold violations), Sign-off extraction (SPEF/QUANTUS/TEMPUS/VOLTUS), Physical verification (DRC/ERC/LVS/ANT), Low power design (UPF), SDC constraint management
Preferred skills
Direct customer contact, Partitioning strategies, Technical specification discussion
Technologies
Cadence Innovus, UPF, SPEF, QUANTUS, TEMPUS, VOLTUS, DRC, ERC, LVS, ANT
Responsibilities
Set up flow for specific library sets and foundry nodes, Drive signoff closure for tape-out, Solve setup and hold violations, Perform sign-off extraction and timing/power analysis, Conduct physical verification and logic equivalent checks
Seniority
Senior, hands-on IC
