Senior Modem SOC Design Engineer - TeraWave
Core
Design digital hardware for the TeraWave satellite communication System on Chip (SOC), focusing on modem datapath, PHY blocks, and Arm compute subsystems.
Role type
Senior IC ASIC/SOC RTL design engineer
Builds
Production silicon for a 6 Tbps satellite communications network
Domain
Space communications / Satellite connectivity
Required skills
RTL design (Verilog/System Verilog), Modem datapath design, PHY block design, Arm compute subsystem design, Signal processing hardware implementation, Microarchitecture definition, SOC integration, Timing closure
Preferred skills
Arm CoreSight debug subsystem design, High-speed memory interface (LPDDR6), Gigabit Ethernet/25G serial interface design, Bus fabric architecture
Technologies
Verilog, System Verilog, Arm, AXI, SRAM, CoreSight, LPDDR6, Ethernet
Responsibilities
Design RTL for modem datapath and PHY blocks; Define microarchitecture from system specifications; Implement signal processing hardware (filters, FFT, FEC); Develop Arm compute subsystem logic; Integrate debug subsystems; Design IO subsystem logic; Support synthesis and timing closure
Seniority
Senior, hands-on IC
