Junior ASIC Backend Engineer
Core
Implementing the physical design phase of ARTPEC SoC chips, including floor-planning, synthesis, timing closure, and power integrity analysis.
Role type
Junior IC ASIC backend engineer
Builds
ARTPEC SoC chips for Axis security and IoT products
Domain
Semiconductor / ASIC design
Required skills
ASIC technologies, EDA tools (floor-planning, synthesis, timing closure), SDC timing constraints, UPF low-power flows, C/Python/TCL scripting
Preferred skills
Knowledge of low-power implementation flows, experience with advanced ASIC technology nodes
Technologies
EDA tools, SDC, UPF, C, Python, TCL
Responsibilities
Top level floorplan and power planning, Subsystem partitioning and macro placement, Block and subsystem physical synthesis, Low power implementation, Top level I/O timing constraints development, Timing optimizations and timing closure, Static and dynamic IR-drop analysis, Equivalence checking, Evaluation of new tools and technologies
Seniority
Junior, hands-on IC
