Physical Design Engineer
Core
Execute and drive all stages of the physical design flow from synthesized netlist to tape-out for complex, high-speed, and low-power ASICs and SoCs.
Role type
Senior IC physical design engineer (SoC/ASIC)
Builds
Production ASICs and SoCs for high-performance computing, AI, mobile, automotive, and data center applications
Domain
Semiconductor / VLSI / ASIC/SoC Physical Design
Required skills
Floorplanning, partitioning, power planning, IR-drop analysis, placement, clock tree synthesis (CTS), routing, timing optimization, timing closure, RC extraction, physical verification, formal verification, ECO implementation, automation scripting
Preferred skills
Cadence Innovus, Synopsys Fusion Compiler, Synopsys PrimeTime SI, Python, Perl, TCL, Shell scripting, C/C++, Linux/Unix, DFT-aware implementation, signal integrity analysis, low-power methodologies
Technologies
Cadence Innovus, Synopsys Fusion Compiler, Synopsys PrimeTime SI, Python, Perl, TCL, Shell, C/C++, Linux, Unix
Responsibilities
Execute placement, CTS, routing, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios; Analyze and resolve timing violations, signal integrity issues, and design rule violations; Develop automation and productivity tools using scripting languages; Collaborate with architecture, RTL, DFT, and verification teams
Seniority
Mid-to-Senior, hands-on IC
