Staff Digital Design Engineer
Core
Execute hands-on digital IP and SoC design, including micro-architecture refinement, RTL implementation, and integration support for automotive networking chips.
Role type
Staff Digital Design Engineer (SoC/IP)
Builds
Reusable, configurable IP blocks and System-on-Chip (SoC) designs for automotive applications
Domain
Semiconductor / Automotive Electronics
Required skills
SystemVerilog/Verilog RTL coding, micro-architecture definition, digital design fundamentals (FSMs, CDC, timing), front-end design flows (lint, synthesis), verification and debug, chip development process knowledge, generator-based RTL flows
Preferred skills
Ethernet protocols knowledge, networking IC development experience, ISO 26262 functional safety familiarity, Python/Tcl/Perl scripting
Technologies
SystemVerilog, Verilog, Python, Tcl, Perl
Responsibilities
Execute hands-on digital IP and SoC design including micro-architecture refinement and RTL implementation; Develop high-quality, synthesizable RTL for reusable IP blocks; Translate IP and SoC roadmap requirements into design plans and deliverables; Drive design quality closure through lint, CDC, RDC, synthesis, DFT checks, and ATPG readiness; Debug and resolve design issues at block, integration, and system levels; Support development and integration of Automotive Base-T1 Ethernet PHYs; Use automated, configurable, generator-based RTL flows to improve reuse and scalability.
Seniority
Staff, hands-on IC
