Physical Design Engineer
Core
Execute and drive all stages of the physical design flow from synthesized netlist to tape-out for complex, high-speed, and low-power ASICs and SoCs.
Role type
Senior IC physical design engineer (SoC/ASIC)
Builds
High-performance computing, AI, mobile, automotive, and data center semiconductor products
Domain
Semiconductor / VLSI / ASIC & SoC Physical Design
Required skills
Floorplanning, partitioning, power planning, IR-drop analysis, placement, clock tree synthesis (CTS), routing, timing optimization, timing closure, RC extraction, physical verification, formal verification, ECO implementation, automation scripting
Preferred skills
Cadence Innovus, Synopsys Fusion Compiler, Synopsys PrimeTime SI, Python, Perl, TCL, Shell scripting, C/C++, Linux/Unix environments, DFT-aware implementation, signal integrity analysis, MMMC sign-off flows
Technologies
Cadence Innovus, Synopsys Fusion Compiler, Synopsys PrimeTime SI, Python, Perl, TCL, Shell, C/C++
