Director High Speed IO Architecture & Design
Core
Lead a Hardware/Digital IP Design Engineering team to develop next-generation high-speed I/O technologies and reusable IP for multi-product roadmaps.
Role type
Director, Hardware/Digital IP Design Engineering
Builds
Reusable IP blocks, high-speed I/O subsystems, and next-generation processor components
Domain
Semiconductor, High-Speed I/O, Digital Hardware Design
Required skills
High-Speed I/O subsystem architecture (SerDes/Chip-To-Chip), Digital IP design leadership, RTL-to-GDSII design flow, Microarchitecture definition, Cross-functional architecture review, Team scaling and management, Silicon debug methodology, Low-power design, Timing closure, Physical design collaboration
Preferred skills
Mixed signal IP experience, Embedded firmware development, Advanced FinFET CMOS node tape-outs, Distributed team leadership, Complex multi-SOC program management
Technologies
SerDes, Chip-To-Chip, RTL, GDSII, FinFET CMOS, SoC, EDA tools
Responsibilities
Provide technical leadership for hardware/digital semiconductor design; Lead and manage System/Digital hardware/front-end designers; Collaborate with architects to translate requirements into microarchitecture; Mentor designers through design reviews and silicon debug; Manage design planning, task assignment, and schedule; Partner with physical-design and verification teams for RTL-to-GDSII delivery; Co-lead silicon-success methodology and post-silicon planning; Establish design-flow best practices and quality standards.
Seniority
Director, hands-on IC with people management
