High‑Speed IP Integration Engineer, Up to Snr Staff (USB/PCIe/UHS) (Hsinchu, Taipei)
Core
Architecting and implementing RTL designs for complex SoC platforms, focusing on the integration and performance evaluation of 3rd party IPs like USB, PCIe, and UHS.
Role type
Senior IC RTL Design Engineer (SoC Integration)
Builds
SoC platforms integrating high-speed interfaces (USB, PCIe, UHS)
Domain
Semiconductor / SoC Design / High-Speed Interfaces
Required skills
Verilog/SystemVerilog, RTL design methodologies, SoC integration, USB/PCIe/UHS IP integration, timing closure, Python/Tcl/Shell scripting
Preferred skills
Low-power design, AMBA protocols (AXI, AHB, APB), post-silicon validation, EDA tools (Synopsys, Cadence)
Technologies
Verilog, SystemVerilog, USB, PCIe, UHS, AMBA, Python, Tcl, Shell, Synopsys Design Compiler, VCS, Cadence
Responsibilities
Define and implement RTL architecture for SoC subsystems, Integrate 3rd party IPs (USB, PCIe, UHS) into SoC designs, Develop and optimize RTL code for performance, power, and area efficiency, Collaborate with verification teams to ensure functional correctness, Work with physical design teams to achieve timing closure, Debug and resolve RTL issues across simulation, emulation, and silicon validation
Seniority
Senior, hands-on IC
