Senior Logic Design Engineer, Cache Coherent Interconnects
Core
Design CPU on-chip and off-chip interconnect networks, MP coherency, and last-level/system caches, including micro-architectural definition, RTL coding, logic debug, synthesis, and timing closure.
Role type
Senior IC logic design engineer (CPU interconnects & caches)
Builds
CPU on-chip and off-chip interconnect networks, MP coherency, and last-level/system caches
Domain
Semiconductor / Computer Architecture
Required skills
Verilog, ASIC design flow, RTL design, logic synthesis, timing analysis, floor-planning, ECO, bring-up & lab debug
Preferred skills
Computer architecture, cache coherency, high speed interconnects, mentoring junior engineers
Technologies
Verilog, RTL, ASIC design flow
Responsibilities
Craft and deliver specific units on the chip; write high performance and low power RTL; perform synthesis and timing closure; collaborate with verification team; work with implementation to meet timing, area, performance, and power goals; assist with timing closure of super units.
Seniority
Senior, hands-on IC
