STA Engineer (M, F, D)
Core
Developing automated block and full chip level signoff flows, ensuring full chip timing/noise convergence and high-quality timing signoff.
Role type
Senior IC Static Timing Analysis (STA) Engineer
Builds
Automated STA flows and timing signoff for high-quality chip designs
Domain
Semiconductor / Digital IC Design
Required skills
Static Timing Analysis (STA), commercial STA tools, hierarchical design flows, power optimization, IP integration, timing constraints development, DFT modes and constraints
Preferred skills
Backend STA closure, AC timing from specs to implementation, noise and signal integrity effects, timing margins from synthesis to signoff, scripting
Technologies
Commercial STA tools, hierarchical design flows, DFT modes
Responsibilities
Developing automated block and full chip level signoff flows, enabling hierarchical timing flows, driving custom IP integration and timing checks, closing work with Design, DFT, architecture, and Power teams
Seniority
Senior, hands-on IC
