ASIC Physical Design
2,686 open positions
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Hardware Technologies PhD Internships AppleUnited States, United States of America 5mo PhD intern contributing to Apple's breakthrough custom silicon and hardware technologies including processors, storage, sensors, and chipsets.
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Chief Architect Texas InstrumentsBengaluru, Karnataka, India 5mo Define and drive long-term System-on-Chip (SoC) and platform architecture roadmaps for high-growth markets including AI-driven data centers and humanoid systems.
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Lead DSP Engineer NxpBangalore 5mo Implement and optimize DSP algorithms and architecture for next-generation automotive-grade Ethernet PHY products.
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ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune) CiscoPune, India 5mo Lead digital design and architecture for high-speed optical interconnects (100G, 200G, 400G) and silicon photonics modules, managing the full ASIC lifecycle from RTL to tapeout.
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Senior ASIC Floorplan Design Engineer NVIDIA2 Locations $196k5mo Design and optimize floorplans for next-generation GPUs and SoCs, influencing early design decisions to solve timing, routing congestion, and area issues.
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MCU Architect, Custom Silicon GlobalFoundriesIND - Karnataka - Bengaluru - Central 5mo Define and drive the architecture of next-generation microcontroller-based silicon solutions, including real-time embedded SoCs and application-specific MCU platforms for industrial, automotive, and infrastructure applications.
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Hardware Engineer (Compute Server) UbiquitiTaipei 5mo Design next-generation high-density storage server solutions (NAS, SAN, unified storage) focusing on system architecture, signal integrity, and thermal management.
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Senior Staff/ Staff Design Engineer SilabsSingapore 5mo Designing digital blocks and SoC infrastructure for low-power MCU and Wireless products.
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Senior Staff Engineer, Physical Design - NoC SiFiveBengaluru, Karnataka, India 5mo Own and drive the implementation of massive, high-bandwidth interconnects (NoC) and Uncore subsystems from RTL to GDSII, acting as a bridge between architecture and physical design to optimize PPA.
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CPU Physical Design Engineer - Cork, Ireland QualcommCork, Ireland 5mo Physical Design Engineer developing and verifying high-performance, low-power CPU designs for Snapdragon SOCs.
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Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology Samsung Electronics3900 N Capital of Texas Hwy, Austin, TX, USA $180k5mo Building highly efficient design and analysis flows and methodologies for Design Technology Co-Optimization (DTCO) to support next-generation SoC products.
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Principal RTL Design Engineer STMicroelectronicsGreater Noida, India 5mo Lead end-to-end RTL design and integration of Core Subsystems and IPs for high-performance, low-power, functionally safe SoCs across multiple generations.
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SR ASIC Design Engineer - NoC & AXI Interconnect Advanced Micro Devices, IncSanta Clara, California 5mo Design and integrate Network-on-Chip (NoC) and AXI/ACE/APB interfaces for high-performance network chips (AINIC and DPU) to achieve first-pass silicon success.
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Logic Design Engineer Quantum MachinesTel Aviv-Yafo, Israel 5mo Designing configurable, low-latency RTL and optimizing FPGA logic & timing for quantum computing control systems.
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SOC Micro-Architect and RTL Designer
MatXMountain View (HQ) or Remote
$160k5mo
Designing high-performance silicon micro-architecture and RTL for compute, memory management, and high-speed connectivity subsystems for AGI training workloads.
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High‑Speed RTL Design Engineer MicronBengaluru, India 5mo Design and implement timing-critical RTL blocks for high-speed memory and storage solutions, ensuring robust logic for synthesis and timing closure.
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Silicon Engineer, Platform and Devices, University Graduate, 2026
GoogleBangalore, Karnataka
5mo
Design, develop, and deploy power and performance optimized chips (ASICs/SoCs) for Google-branded consumer devices, focusing on imaging, machine learning, video, and security.
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PCIe design Architect BroadcomIND-Bangalore Electronic City - S1 5mo Designing and architecting PCIe subsystems and SoCs for Broadcom products.
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<GPU>GPU IC Design and Integration Engineer MediaTekHsinChu 5mo GPU IC design and integration focusing on digital design flow, low power analysis, and post-silicon debugging.
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Senior Hardware Design Engineer, High Speed Networking Arista-NetworksNashua, NH, us 6mo Designing high-speed networking and Ethernet products for enterprise campuses, hyperscale datacenters, and AI clusters.
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Hardware Design Engineer TensordyneRemote 6mo Design and develop hardware systems for custom AI ASICs and generative AI inference products, covering schematics, PCB layout, and mechanical design.
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Senior Staff ASIC Design Engineer AxiadoHyderabad, TS, in 6mo Design and implement System-on-Chip (SoC) micro-architecture, RTL coding, synthesis, and timing closure for secure AI infrastructure.
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AMBA Architect ArmCambridge, United Kingdom 6mo Designing next-generation Arm system architectures focusing on memory systems, address translation, and virtualization-aware interfaces.
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Senior/Staff Digital Design Engineer OlixAustin, TX 6mo Architect, design, and implement high-throughput digital pipelines for real-time data-processing silicon in advanced CMOS nodes.
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Senior ASIC Design Engineer – Processor Subsystem EspaceSaratoga, CA 6mo Design, configuration, integration, and verification planning of Arm processor IP and associated subsystem components for satellite IoT connectivity ASICs.
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Principal System Engineer (f/m/d) Renesas-ElectronicsRemote 6mo Define and drive the system architecture of next-generation sensor IC solutions for automotive and industrial markets, translating system requirements into silicon architectures.
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