EDA Methodology Architect
Core
Define and own the next generation RTL2GDS flow for advanced nodes (3nm and below) and high performance GPU, CPU and SoC designs, acting as a bridge between core engine developers and design teams.
Role type
Senior IC EDA Methodology Architect (Physical Design)
Builds
Scalable, maintainable RTL2GDS flows and frameworks for VLSI design teams
Domain
Semiconductor / VLSI Physical Design / EDA
Deliverable
production ML models
Required skills
Physical design flow expertise (RTL, DFT, synthesis, placement, CTS, routing, signoff), Python, Perl, TCL, A/B testing design, QoR analysis, root-cause analysis, PPA optimization
Preferred skills
AI/ML or GenAI application to physical design, advanced-node design experience, core engine development collaboration
Technologies
ICC2, Innovus, PrimeTime, Tempus, Python, Perl, TCL
Responsibilities
Define real-world optimization problems and roadmaps for P&R engines; Refactor legacy flows into scalable frameworks; Design and run A/B experiments and develop analytics to mine QoR datasets; Perform root-cause analysis on timing closure and performance limiters; Partner with architecture, RTL, and CAD teams to drive tool adoption; Drive aggressive PPA and schedule targets
Seniority
Senior, hands-on IC
