ASIC Physical Design
2,686 open positions
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Manager, Physical Design Circuit and Signoff CAD NVIDIAIsrael, Yokneam 4mo Lead a team responsible for tracking and executing end-to-end activities spanning internal CAD flow development and circuit-level studies to support silicon sign-off for NVIDIA's advanced chips.
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SoC Design Engineer ArmBudapest, Hungary 4mo Designing and integrating RTL subsystems and microarchitecture for complex System-on-Chip (SoC) processing systems.
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Principal Design Engineer MicronSan Jose, CA $198k4mo Designing and implementing advanced ASIC micro-architectures for next-generation solid-state drive controllers.
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Digital Senior Design Engineer CienaOttawa CA$109k4mo Design power and area optimized functional blocks for Ciena's Wavelogic optical fiber transmission products.
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Staff/Senior Staff Physical Design Engineer (Technical Lead) Enchargeai36Remote 4mo Lead physical design for next-generation in-memory computing silicon products, optimizing PPA for edge-to-cloud applications.
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CAD Engineer - Static Timing Analysis & Physical Design AppleHaifa, Israel 4mo Develop and support advanced Static Timing Analysis (STA) flows and methodologies to deliver robust timing closure solutions for cutting-edge silicon designs.
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Chip Lead NxpAustin (Oakhill, Office) 4mo Lead product execution and architecture definition for Automotive ASIL-B/D SoCs and Data Center SOCs, ensuring safety mechanisms, high reliability, and low defectivity.
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Staff Engineer, Digital Design Engineering AnalogdevicesIndia, Bangalore, RMZ 4mo Lead the development, curation, and delivery of reusable strategic digital IPs (accelerators, datapath, high-speed interfaces) to accelerate product development across business units.
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Micro-Architect and RTL Designer
MatXMountain View (HQ) or Remote
$160k4mo
Designing high-performance silicon micro-architecture and RTL for compute, memory management, and high-speed connectivity blocks to support AGI workloads.
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Principal Digital Design Engineer ON SemiconductorCo. Limerick, Ireland 4mo Lead digital design architecture, RTL implementation, and low-power design for power management ICs serving consumer, industrial, and automotive applications.
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EDA Tools Hardware Engineer IntelUS, California, Santa Clara $142k5mo Develop and maintain full-chip physical implementation flows, including floor planning, hierarchical block integration, placement, routing, power grid planning, and clock tree synthesis to enable scalable SoC assembly.
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Static Timing Analysis (STA) Engineer AlteraToronto, Ontario, Canada CA$103k5mo Execute static timing analysis and support timing closure for advanced FPGA designs to ensure high-performance, power-efficient outcomes.
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ASIC Principal Design Engineer HpeBengaluru, Karnātaka, India 5mo Architecting high-performance blocks and defining micro-architecture for advanced networking ASICs to deliver maximum throughput and minimum power.
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Senior FPGA Engineer (DV Equities) DvtradingLondon 5mo Architect and deliver ultra-low-latency FPGA trading systems for global equity and futures markets to provide a competitive edge in market making.
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Physical Design Engineer CerebrasHeadquarters/Sunnyvale Office $230k5mo Design and analysis of 3D integrated products, combining traditional ASIC/SoC physical design with packaging, power, clock, and cooling analysis.
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Distinguished Technologist - Memory/Storage Utilization & Data Placement Architect HpSpring, Texas, United States of America $190k–$274k5mo Define unified memory/storage hierarchy and data placement strategies for AI workloads, optimizing performance across DRAM, SSD, and cache layers.
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Digital IC designer - Image processor MediaTekHsinChu 5mo Design industry-leading image signal processors (ISP) for diverse products including smartphones, tablets, automotive, and home entertainment.
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Sr Principal Engineer AI/ML GlobalFoundriesSanta Clara, US $171k5mo Designing and leading the RTL development of an AI-enabled RISC-V CPU core, including vector extensions and matrix engines for physical AI applications.
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Experienced Digital Design Engineer Texas InstrumentsRa'anana, Israel 5mo Define, develop, and debug silicon micro-architecture design for wireless MCU products targeted at Industrial markets.
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Sr. EMIR Engineer, Annapurna Labs - Cloud Scale Machine Learning
AmazonCupertino, California, United States
$159k5mo
Design and analyze power grids for SoCs, developing test cases to model demand currents and sign off EMIR analysis taking into account board and package impact.
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FPGA Build System Engineer - Engineering Productivity - Sydney Arista-NetworksSydney, NSW, au 5mo Design, optimize, and maintain build systems and CI/CD pipelines for FPGA development workflows to ensure scalability, reliability, and performance.
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CPU Microarchitect/RTL design Engineer, Senior/Staff - Cork, Ireland QualcommCork, Ireland 5mo Design CPU microarchitecture and RTL for high-performance, low-power devices, collaborating with chip architects on product definition and lifecycle.
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