Senior Staff ASIC Design Engineer
Core
Design and implement System-on-Chip (SoC) micro-architecture, RTL coding, synthesis, and timing closure for secure AI infrastructure.
Role type
Senior Staff ASIC Design Engineer
Builds
Trusted Control/Compute Units (TCU) combining hardware security, AI resilience, and real-time platform management
Domain
Semiconductor / Hardware Security / AI Infrastructure
Deliverable
production ML models
Required skills
RTL logic design, Verilog coding, micro-architecture specification, RTL synthesis, timing closure, interface protocols (PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, SPI), FPGA emulation debug, scripting (Perl, Python), tape-out cycle experience
Preferred skills
Silicon bring-up and debug, repository management (Bitbucket/Jenkins), bug tracking (JIRA)
Technologies
Verilog, Perl, Python, HAPS, Veloce, PCIe, USB, Ethernet, DDR, I2C, I3C, eSPI, SPI, Bitbucket, Jenkins, JIRA
Responsibilities
Develop SoC design and implementation/integration; Write efficient RTL code and micro-architecture specifications; Perform synthesis and timing closure; Support prototyping, test program development, chip validation, and production maturity; Collaborate with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams; Debug on FPGA-based emulation platforms
Seniority
Senior Staff, hands-on IC
