Logic Design Engineer
Core
Designing configurable, low-latency RTL and optimizing FPGA logic & timing for quantum computing control systems.
Role type
Senior IC logic design engineer (FPGA/RTL)
Builds
State-of-the-art control and orchestration platform for quantum computers
Domain
Quantum computing hardware control
Required skills
RTL coding, System Verilog, FPGA logic optimization, timing optimization, UVM (implied by VCS/Vivado context), architecture design
Preferred skills
Quantum physics collaboration, cross-disciplinary teamwork
Technologies
System Verilog, VCS, Vivado
Responsibilities
Design low-latency configurable RTL, Optimize FPGA logic and timing, Own end-to-end coding process from architecture to implementation, Collaborate with quantum physicists and other engineers
Seniority
Mid-Senior, hands-on IC
