Principal RTL Design Engineer
Core
Lead end-to-end RTL design and integration of Core Subsystems and IPs for high-performance, low-power, functionally safe SoCs across multiple generations.
Role type
Principal RTL Design Engineer (SoC)
Builds
Core Subsystems, ARM-based SoCs, Interconnect Fabrics, Memory Controllers
Domain
Semiconductor / ASIC Design
Required skills
RTL design, SoC-level integration, ARM architecture, AMBA protocols (AXI, AHB, APB), clock/reset domain management, memory subsystems, EDA tools (synthesis, LINT, CDC, STA), Python scripting, safety-critical design flows
Preferred skills
Automotive Functional Safety (ISO26262), formal verification, static/dynamic power checks, patent/publication experience
Technologies
ARM Cores, AHB/AXI, RAM, Flash, Python, LINT, CDC, Synthesis, DFT, Static Timing Analysis
Responsibilities
Define high-level SoC specifications with architects; Own end-to-end IP/Sub-system RTL delivery; Lead RTL design for complex multi-core architectures; Drive Safety, Security, and Debug architecture development; Engage cross-functionally for silicon bring-up and debug; Mentor junior engineers and provide technical leadership.
Seniority
Principal, hands-on IC with mentorship
