Senior SOC Physical Design Engineer, HBM
Core
Drive physical implementation of advanced high-bandwidth memory (HBM) system-on-chip (SoC) logic and base die designs from netlist through GDSII.
Role type
Senior IC physical design engineer (HBM/SoC)
Builds
Heterogeneous integration of HBM SoC blocks and top-level integration for tapeout
Domain
Semiconductor / Memory / SoC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static timing analysis, clocking concepts, Synopsys Design Constraints (SDC), power intent methodologies (UPF/CPF), physical verification flows (DRC/LVS), hierarchical physical design, SoC integration methodologies
Preferred skills
HBM or DRAM adjacent SoC design experience, signal integrity and reliability analysis (IR drop, electromigration), Tcl/Python scripting for automation
Technologies
Innovus, Fusion Compiler, IC Validator (ICV), Calibre, PrimeTime, Tempus, Ansys
Responsibilities
Support physical implementation of SoC blocks from floorplanning through placement, CTS, routing, and optimization; Assist with setup and hold timing closure across multi-mode, multi-corner scenarios; Collaborate with RTL design teams to ensure correct clocking, reset strategies, and power intent implementation; Integrate and implement complex IP blocks including controllers, interfaces, MBIST, DFT logic, buffers, and PHY-adjacent logic; Run and debug physical signoff checks (DRC, LVS, timing signoff) and address violations; Work with DFT teams to ensure scan and MBIST logic are physically clean; Participate in tapeout readiness activities including ECO flows, checklists, design reviews, and post-silicon debug
Seniority
Senior, hands-on IC
