SoC Power Architecture Engineer - Processor Subsystem
Core
Define, design, and implement power domain architectures for ASIC-based processor subsystems targeting satellite IoT connectivity applications, focusing on aggressive duty cycling and ultra-low standby power.
Role type
SoC Power Architecture Engineer
Builds
ASIC-based processor subsystems for satellite IoT end-node devices
Domain
Space communications / Satellite IoT / Low-power ASIC design
Deliverable
production ML models | product features | infrastructure
Required skills
Power domain partitioning, UPF (IEEE 1801) power intent, RTL design (SystemVerilog/VHDL), low-power synthesis constraints, power control sequencing, retention architecture, isolation strategies, level shifters, power switches
Preferred skills
Arm Corstone processor subsystem IP, AMBA bus protocols (AHB, APB, AXI), power analysis tools (PrimeTime PX, Joules), PMIC interface design, energy-harvesting constraints
Technologies
UPF, IEEE 1801, SystemVerilog, VHDL, Arm Cortex-M, AMBA, Synopsys PrimeTime PX, Cadence Joules
Responsibilities
Define and architect power domains (always-on, switchable, retention); Design power domain partitioning for embedded processors and bus interconnects; Develop logic for power domain separation (switches, isolation cells, level shifters); Implement power control sequencing and state machines for wake-up latency; Collaborate on UPF intent capture; Define low-power modes (Sleep, Deep Sleep, Power-Off); Support power-aware synthesis, place-and-route, and sign-off flows; Review power intent files for RTL consistency; Engage verification teams for low-power mode validation
Seniority
Senior, hands-on IC
