SR ASIC Design Engineer - NoC & AXI Interconnect
Core
Design and integrate Network-on-Chip (NoC) and AXI/ACE/APB interfaces for high-performance network chips (AINIC and DPU) to achieve first-pass silicon success.
Role type
Senior IC ASIC Design Engineer (NoC & Interconnect)
Builds
Front-end RTL designs for network-on-chip and interconnect IP
Domain
Semiconductor / ASIC Design
Required skills
SystemVerilog/Verilog RTL design, NoC architecture, AXI/ACE/APB interface design, queuing system design, VCS simulation, Perl/Python/Shell scripting
Preferred skills
NoC protocol knowledge, buffer management, RTL design verification
Technologies
VCS, SystemVerilog, Verilog, Perl, Python, Shell
Responsibilities
Design and integrate NoC and AXI/ACE/APB interfaces, implement queuing systems, collaborate with architecture/IP/physical design teams, support post-silicon bring-up and yield learning
Seniority
Senior, hands-on IC
