Senior Physical Design Engineer
Core
Drive physical design and timing closure from netlist to GDS, integrating analog IOs and macros for GPU chips.
Role type
Senior Physical Design Engineer (IC Design)
Builds
GPU chips and related hardware components
Domain
Semiconductor / VLSI Design
Deliverable
production ML models
Required skills
Physical design flow, Timing closure, DRC/ERC/LVS verification, RC extraction, IR drop analysis, EM analysis, Synopsys/Cadence tools, Constraint creation, ECO implementation, Formal verification, Automation scripting
Preferred skills
Scan insertion, DFT knowledge
Technologies
Synopsys, Cadence
Responsibilities
Drive physical design and timing from netlist to GDS; Partner with mixed signal teams to integrate Analog IOs and macros; Perform Physical verification (DRC, ERC, LVS, Antenna checks); Debug timing violations and implement functional/Timing ECOs; Create and update timing constraints with front-end teams; Perform multi-mode/multi-corner timing closure and analysis.
Seniority
Senior, hands-on IC
