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Senior Physical Design Engineer

US, CA, Santa Clara💼 Full-time💰 $168,000–$168,000🗓 2026-05-14 → 2026-09-25

Core

Responsible for all aspects of physical design and implementation of GPU and other ASICs for desktop, laptop, workstation, and mobile markets.

Role type

Senior Physical Design Engineer (ASIC/GPU)

Builds

GPU and ASIC chips

Domain

Semiconductor / VLSI / Hardware

Deliverable

production ML models

Required skills

VLSI physical design implementation, chip floorplanning, power/clock distribution, place & route (P&R), timing closure, static timing analysis, power and noise analysis, back-end verification, custom macro block design (RAMs, CAMs, high-speed IO drivers, PLLs), CAD tool proficiency (Synopsys, Cadence, Mentor Graphics), scripting (Python, Perl, Tcl, Make)

Preferred skills

Power, Performance, and Area (PPA) improvement initiatives

Technologies

Synopsys ICC2/DC/PT/STAR-RC/ICV, Cadence Innovus/Tempus/SeaHawk, Mentor Graphics

Responsibilities

Establish physical design methodologies and flow automation, perform chip assembly and P&R, ensure timing closure, craft designs for static timing analysis, power and noise analysis, and back-end verification

Seniority

Senior, hands-on IC

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