Senior/Staff Digital Design Engineer
Core
Architect, design, and implement high-throughput digital pipelines for real-time data-processing silicon in advanced CMOS nodes.
Role type
Senior/Staff Digital Design Engineer (ASIC/SoC)
Builds
High-speed, real-time data-processing silicon chips (ASICs/SoCs)
Domain
Semiconductor hardware design (Digital CMOS, High-Speed Interfaces)
Deliverable
production ML models
Required skills
CMOS digital design, RTL development (SystemVerilog/Verilog/VHDL), FPGA prototyping, timing closure (STA), high-speed IP integration (SerDes, HBM/DDR, PCIe), algorithm modeling (MATLAB/Simulink/Python), power-performance-area (PPA) optimization
Preferred skills
Tape-out experience on advanced nodes, coherent optical links knowledge, AI/ML workload architecture familiarity
Technologies
Xilinx/AMD/Intel FPGA, SystemVerilog, Verilog, VHDL, MATLAB, Simulink, Python, NumPy, UPF/CPF, EDA flows
Responsibilities
Architect and implement high-throughput digital pipelines; prototype and iterate in FPGA; model algorithms and validate concepts; own RTL development including synthesis and verification; analyze PPA; collaborate with optical/mixed-signal teams; mentor junior engineers
Seniority
Senior/Staff, hands-on IC with mentorship
