Senior/Staff Design Engineer
Core
Developing and owning RTL development of AI-enabled RISC-V CPU cores, focusing on micro-architecture, performance, power, and area optimization.
Role type
Senior/Staff IC CPU IP Design Engineer
Builds
RISC-V Vector CPU cores, custom extensions, and AI-enabled Matrix engines
Domain
Semiconductor / CPU Microarchitecture / RISC-V
Deliverable
production ML models
Required skills
CPU pipeline stages (in-order/out-of-order), microprocessor architecture (fetch/decode, branch prediction, scheduling, register renaming, ROB, out-of-order execution, integer/floating-point execution, load/store, prefetch, vector data path, cache/memory), System Verilog/Verilog/VHDL, simulator and waveform debugging, logic design principles, timing and power implications
Preferred skills
RISC-V/ARM/MIPS CPU design, hardware multi-threading, virtualization, SIMD designs, vector/matrix-enabled CPUs, high-performance microarchitecture trade-offs, low-power microarchitecture, scripting (Perl/Python), cache coherency, memory consistency, SoC integration, safety/security microarchitecture
Technologies
System Verilog, Verilog, VHDL, Perl, Python
Responsibilities
Drive micro-architecture and design of critical CPU core blocks; Design RISC-V Vector CPU core and custom extensions; Design AI-enabled Matrix engine; Explore high-performance strategies with modeling team; Perform microarchitecture development from architectural exploration to detailed specifications; Configure design features for power/performance/area/timing goals; Support functional verification and RTL performance validation; Partner on physical design aspects (timing, area, reliability, testability, power)
Seniority
Senior/Staff, hands-on IC
