Sr. EMIR Engineer, Annapurna Labs - Cloud Scale Machine Learning
Core
Design and analyze power grids for SoCs, developing test cases to model demand currents and sign off EMIR analysis taking into account board and package impact.
Role type
Senior IC physical design engineer (power integrity)
Builds
Inferentia and Trainium SoCs for AI workloads in datacenters
Domain
Semiconductor hardware design (ASIC) / Power Integrity
Deliverable
production ML models | infrastructure
Required skills
EMIR analysis tools (Redhawk-SC, Voltus), circuit-level power/EM/IR understanding, scripting (Tcl, Perl, Python), physical design, thermal analysis, post-silicon power measurement
Preferred skills
RTL design (System Verilog), PnR tools (FusionCompiler, Innovus), power analysis tools (PrimePower), timing analysis tools (PrimeTime), automation (Make)
Technologies
Redhawk-SC, Voltus, FusionCompiler, Innovus, PrimePower, PrimeTime, System Verilog, Tcl, Perl, Python
Responsibilities
Design and evaluate power grids, develop vectors for IR and thermal analysis, root cause low switching coverage, maintain dashboards for EMIR status, combine IR analysis of SoC with board/package level, correlate simulation with post-silicon measurements, partner with EDA vendors on new methodologies
Seniority
Senior, hands-on IC
