Senior STA Engineer, Sub-chip
Core
Senior Static Timing Analysis (STA) engineer responsible for full timing signoff, convergence, and quality approval from pre-layout through signoff for complex chiplet and full-chip networking devices.
Role type
Senior IC physical design engineer (static timing analysis)
Builds
High-speed communication chips (networking silicon)
Domain
Semiconductor / Networking / Physical Design
Deliverable
production ML models
Required skills
Static Timing Analysis (STA), Prime Time, SDC generation, timing path debugging, chiplet design, full-chip timing, timing optimization, convergence management
Preferred skills
AI tools orientation, Agentic Frameworks, AI prompting, Linux environments, TCL, Python, shell scripting, data collection and analysis
Technologies
Prime Time, SDC, Linux, TCL, Python
Responsibilities
Perform advanced AI Static Timing Analysis for complex chiplet and full chip level; Run and build STA tools for analysis and debug timing; Use traditional STA tools to review and debug timing paths, understand constraints, and generate SDC and timing ecos; Identify convergence risks and work closely with physical design, RTL and DFT teams; Responsible for full timing closer and quality approval from pre-layout STA model through signoff.
Seniority
Senior, hands-on IC
