Senior Synthesis CAD Engineer
Core
Architect, build, and improve advanced RTL to PNR tools, flows, and methodologies for high-speed communication devices.
Role type
Senior IC physical design tool engineer (synthesis)
Builds
RTL to PNR tools, flows, and methodologies
Domain
Semiconductor / VLSI / EDA
Required skills
VLSI synthesis flows, Synopsys Fusion Compiler, Design Compiler, Tcl scripting, Python scripting, PPA optimization, flow integration
Preferred skills
Place and Route (P&R) flows, Static Timing Analysis (STA), AI/ML automation in production runs, methodology definition
Technologies
Synopsys Fusion Compiler, Design Compiler, Tcl, Python, AI/ML
Responsibilities
Design and refine sophisticated Synthesis flows to meet PPA objectives; Partner with Front-End Design and P&R teams to define boundaries and resolve constraints; Develop robust Tcl/Python scripts to improve Flow Turnaround Time (TAT); Provide deep-dive debugging of complex tool failures and formal synthesis training.
Seniority
Senior, hands-on IC
