CAD Engineer - Static Timing Analysis & Physical Design
Core
Develop and support advanced Static Timing Analysis (STA) flows and methodologies to deliver robust timing closure solutions for cutting-edge silicon designs.
Role type
Senior IC physical design engineer (static timing analysis)
Builds
Automated STA flows, timing databases, and Python-based tools for timing analysis and ECO automation
Domain
Semiconductor physical design / Static Timing Analysis
Required skills
PrimeTime, Python, setup/hold analysis, clock domain crossing, OCV, statistical timing analysis, RTL-to-GDSII flow, power-aware timing analysis
Preferred skills
SQL (MySQL, PostgreSQL), advanced timing concepts (multicycle paths, false paths, timing exceptions)
Technologies
PrimeTime, Python, MySQL, PostgreSQL
Responsibilities
Develop and maintain automated STA flows from constraint generation to signoff reporting; Build and optimize timing databases for cross-project analysis; Create Python-based tools for constraint validation and ECO automation; Collaborate with design teams to debug timing violations; Interface with EDA vendors on tool bring-up and feature adoption; Support multiple projects during timing closure and tapeout phases
Seniority
Senior, hands-on IC
