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Hardware & Physical Engineering
› Analog IC Design
Analog IC Design
1,386 open positions
Principal Engineer, Power Management IC Designer
Renesas-Electronics
Morrisville, North Carolina , us
4mo
Lead a design team to develop innovative, high-performance Power Management ICs for Space markets, including DC-DC switching converters, LDOs, and multi-function power management circuits.
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Hardware Engineer
Broadcom
USA-CA Irvine Alton Parkway Bldg 1
$108k–$108k
4mo
Evaluate silicon technology in advanced process nodes to define new technology platforms and assess design-process interactions for IP and product designs.
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Senior Engineer
Arm
Bengaluru, India
4mo
Define, design, and verify package designs for 2.5D and 3D package systems, focusing on Signal and Power Delivery Networks.
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Junior Hardware Engineer - Signal & Power Integrity - Israel - ETR
Cisco
Caesarea, Israel
4mo
Design and analyze high-speed analog/digital signals for networking products, focusing on signal and power integrity of ASICs, packages, and PCBs.
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Principal / Senior / Engineer, TCAD DRAM
Micron
Hiroshima - Fab 15, Japan
4mo
Physics-based device simulation and modeling of advanced semiconductor devices (DRAM, CMOS) to support technology development and predict device behavior.
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Principal Engineer- HIG HBM Layout
Micron
Hyderabad - Phoenix Aquila, India
4mo
Designing and developing complex Application-Specific Integrated Circuits (ASICs) for High Bandwidth Memory (HBM) products serving AI and high-performance computing applications.
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Staff Engineer, HIG HBM Layout
Micron
Hyderabad - Phoenix Aquila, India
4mo
Design and development of critical analog, mixed-signal, and custom digital blocks with full chip-level integration support for High Bandwidth Memory (HBM) used in AI and high-performance computing.
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Staff Memory Design Engineer, HBM
Micron
Richardson, TX
4mo
Designing and optimizing digital, analog, and memory core circuits for advanced DRAM products from concept to silicon.
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STAFF ENGINEER, MODULE HW VAL
Micron
Hyderabad - Phoenix Aquila, India
4mo
Lead end-to-end module-level competitor analysis for DRAM memory products, including teardowns, reverse engineering, and benchmarking against industry standards.
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Staff Engineer, HIG HBM Layout
Micron
Hyderabad, Telangana, India
4mo
Design and development of critical analog, mixed-signal, custom digital blocks and full chip level integration for High Bandwidth Memory (HBM) used in AI and high-performance computing.
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Staff Electronics SI/PI Engineer
Arm
Bengaluru, India
4mo
Perform system-level signal integrity (SI) and power integrity (PI) analysis for System-on-Chip (SoC) to board integration, focusing on hardware platform prototypes for Arm processors.
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Principal Engineer- HIG HBM Layout
Micron
Hyderabad, Telangana, India
4mo
Designing and developing complex Application-Specific Integrated Circuits (ASICs) for High Bandwidth Memory (HBM) products serving AI and high-performance computing applications.
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Senior Electronics SI/PI Engineer
Arm
Bengaluru, India
4mo
Perform system-level signal integrity (SI) and power integrity (PI) analysis for SoC-to-board integration, optimizing routing strategies and power delivery networks for high-performance compute platforms.
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Інженер (IC Layout Engineer) групи аналогового дизайну
Bosch-Group
Remote
4mo
IC Layout Engineer responsible for developing analog topological elements/modules, ensuring DRC/LVS compliance, and supporting the tape-out process for semiconductor chips.
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Director, Power MOSFET Technology Development
ON Semiconductor
Scottsdale, AZ, United States
4mo
Lead the development and qualification of cutting-edge silicon Power MOSFET technologies for AI factories and automotive power conversion applications.
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Lead Principal Engineer, Layout Design
Micron
Tlaquepaque, Jalisco, Mexico
4mo
Lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts.
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Analog Layout Designer
Broadcom
USA-CA Irvine Alton Parkway Bldg 2
$108k–$108k
4mo
Analog layout designer providing onsite support for advanced nodes, working with global layout and design team.
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Senior Manager, Analog and Mixed Signal Design Engineering
Analogdevices
India, Bangalore, RMZ
4mo
Lead a small team of analog/mixed-signal IC designers while serving as the technical lead for block definition, design execution, and subsystem integration.
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Senior Mixed Signal Design Engineer
NVIDIA
Taiwan, Taipei
4mo
Designing high-speed memory I/O interfaces and solving circuit design challenges in deep submicron CMOS FinFET processes for NVIDIA's GPU and AI products.
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Lead Principal Engineer, Layout Design
Micron
Jalisco, Mexico
4mo
Lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts.
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PMTS Photonics Packaging Design Integration
GlobalFoundries
USA - Vermont - Essex Junction
$132k–$132k
4mo
Lead development and sustainment of advanced optical packaging solutions for silicon photonics (SiPh) and co-packaged optics (CPO) platforms, focusing on thermal, mechanical, electrical, and optical chip package co-design.
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Engineer, HIG HBM Layout
Micron
Hyderabad, Telangana, India
4mo
Design and development of critical analog, mixed-signal, custom digital blocks and full chip level integration for High Bandwidth Memory (HBM) used in AI and high-performance computing.
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Photonic Design Automation Engineer
PsiQuantum
Palo Alto, California, United States
$130k–$130k
4mo
Own and scale the layout-to-netlist and multi-physics integration flow for a silicon photonics platform to enable reliable photonic IC tape-outs.
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Senior EM/IR Engineer
Espace
Saratoga, CA
4mo
Design, simulate, and verify high-performance digital, analog, and RF integrated circuits for 5G, IoT, and satellite communications applications.
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Staff Engineer Design
Micron
Hyderabad - Phoenix Aquila, India
4mo
Block and sub-system level design and timing optimization for memory and storage solutions, supervising layout and collaborating on full-chip floorplanning.
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Staff Engineer Design
Micron
Hyderabad, Telangana, India
4mo
Lead block and sub-system level design, timing optimization, and full-chip floorplanning for memory and storage solutions.
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Senior Engineer - Standard Cell Design
Micron
Hyderabad - Phoenix Aquila, India
4mo
Design and maintain standard cells for new DRAM products on new technology, collaborating with DTCO teams to develop architectures and characterization models.
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Field Application Engineer Intern (Hardware)
Marvell
Shanghai
4mo
Intern supporting customer engagements, debugging hardware/software systems, and optimizing optical interconnect product performance.
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Mixed Signal Logic Design Engineer
Intel
Malaysia, Penang
4mo
Develops logic design, RTL coding, and simulation for mixed-signal and high-speed IPs to generate cell libraries, functional units, and subsystems for full chip integration.
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Senior Engineer, Analog Layout
Renesas-Electronics
Remote
4mo
Senior Analog Layout Engineer developing floor plans, routing, and verification for PMICs, Linear, and Switching DC-DC converters powering next-gen phones and handheld devices.
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Senior Mixed Signal Design Engineer
NVIDIA
US, CA, Santa Clara
$196k–$196k
4mo
Senior Mixed Signal Design Engineer developing high-speed interfaces and analog circuits for next-generation NVLink, serving consumer graphics, self-driving cars, and AI product lines.
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Layout Designer
Texas Instruments
Tucson, AZ, United States
4mo
Development and preparation of multi-dimensional layouts and detailed drawings of semiconductor devices from schematics and geometry.
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Signal Integrity Engineer
Hpe
Sunnyvale, California, United States of America
$174k–$353k
4mo
Perform high-speed ASIC PAM4 SerDes and system-level signal and power integrity analysis for cutting-edge networking product design.
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Senior Mixed Signal Design Engineer
NVIDIA
US, CA, Santa Clara
$168k–$168k
4mo
Senior engineer developing high-speed electrical/optical interfaces and analog circuits for next-generation NVLINK, supporting products from consumer graphics to self-driving cars and AI.
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Electrical/Optical SerDes Analog Mixed Signal Design Engineer
MediaTek
Irvine, CA
4mo
Design and verification of high-speed electrical and optical transceivers for data centers, cloud infrastructure, and AI/HPC systems.
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Senior Mask Design Engineer - Hardware
NVIDIA
US, CA, Santa Clara
$132k–$132k
4mo
Senior Mask Layout Design Engineer performing physical layout for high-speed mixed-signal circuits (PLLs, SerDes, ADCs, ESD) in sub-micron CMOS technologies.
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R&D Engineer IC Design
Broadcom
USA-CA San Jose Innovation Drive
$120k–$192k
4mo
Designing cutting-edge CoWoS 2.5D/3D interposer designs for high-speed interfaces, including custom routing, bump map design, and physical verification for enterprise and mega-scale data center network switches.
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Engineer, DEG Layout
Micron
Bengaluru, India
4mo
Design and develop analog, mixed-signal, custom digital block, standard cells, and full chip layouts for memory and storage solutions.
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Memory Design Engineer, HBM
Micron
Richardson, TX
4mo
Designing and analyzing digital and analog circuits for advanced memory products, specifically DRAM, from concept to silicon solution.
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ENGR STAFF, ANALOG; DSGN
ON Semiconductor
Bangalore, Karnataka, India
4mo
Design and develop high-performance, reliable non-volatile memory (NVM) IPs for automotive and industrial systems.
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Principal Analog Layout Engineer
Ciena
Ottawa
$138k–$138k
4mo
Develop block and macro level layouts for high-speed analog circuits (DAC, ADC, SERDES) in deep-submicron CMOS/BiCMOS technologies for optical fiber transmission solutions.
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Foundry Virtuoso Engineer
Cadence
SHANGHAI 08
4mo
Provide technical support for Virtuoso-based analog backend flows, including schematic, layout, and design environment usage, while assisting foundry teams in developing and maintaining technology files and PCells.
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CMOS Device Integration Team - DMTS
Micron
Boise, ID - Main Site
4mo
Leading CMOS device and module development for next-generation DRAM, HBM, and Compute-in-Memory architectures to enable AI and high-performance computing.
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SI/PI Engineer
Etched
San Jose
5mo
Own SI/PI methodology for high-speed PCB and system designs ensuring electrical margins for multi-gigabit interfaces.
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ASIC Package Engineer
Cisco
Taipei, Taiwan
5mo
Perform mechanical and thermomechanical simulations of ASICs and complex silicon packages to ensure reliability and accelerate product design.
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Mechanical Engineering Technical Leader
Cisco
Taipei, Taiwan
5mo
Perform finite element analysis and thermomechanical simulations for ASIC packages, substrates, and advanced packaging assemblies to ensure mechanical reliability and support product design.
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Lead Customer Engagement Engineer - Voltus
Cadence
SHANGHAI
5mo
Enables EM/IR and thermal signoff technologies for Foundry PDK and Design Service teams through techfile development and reference flow creation.
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STAFF ENG-HIG-HBM-LAYOUT
Micron
Hyderabad - Phoenix Aquila, India
5mo
Lead the layout design and development of complex analog, mixed-signal, and digital blocks and full chip level integration for memory and storage solutions.
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Process Integration Engineer | APTD
Micron
Boise, ID - Main Site
5mo
Developing and enabling deployment of advanced interconnect technologies and packaging solutions to meet performance, cost, and manufacturability requirements for next-generation semiconductor products.
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Senior Manager IP Design
Micron
Hyderabad, Telangana, India
5mo
Leading an IP circuit design group in India to develop critical analog and digital IP circuits for DRAM memory products.
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