Logic Designer
Core
Designing digital logic and DSP algorithms for mixed-signal IP blocks including high-speed SerDes, ADC/DAC digital, calibration engines, and control logic.
Role type
Senior IC mixed-signal logic/DSP design engineer
Builds
Mixed-signal subsystems (calibration state machines, digital filters, adaptive equalization, clock/data recovery loops)
Domain
Semiconductor / Analog Mixed Signal SerDes
Deliverable
production ML models | product features
Required skills
RTL design (Verilog), RTL-to-gate synthesis, timing closure, low-power design, DSP fundamentals (filtering, sampling, quantization, timing recovery), mixed-signal verification (AMS simulation, Verilog-AMS)
Preferred skills
High-speed interface standards (SerDes, PCIe, DisplayPort, Ethernet), calibration/adaptation algorithms for ADCs/DACs/equalizers, static timing analysis (STA), analog-digital co-design
Technologies
Verilog, Verilog-AMS
Responsibilities
Design and implement digital logic for mixed-signal subsystems; Collaborate with analog teams to define digital-analog interfaces and control logic; Perform synthesis, timing closure, and low-power optimization; Build and maintain block-level verification environments; Support silicon bring-up and debug by correlating digital logic with analog measurements; Mentor junior engineers on digital design practices
Seniority
Senior, hands-on IC