Senior Standard Cell Library Engineer
Core
Design, characterize, and test leading-edge standard cells to enable customers with robust semiconductor solutions.
Role type
Senior IC standard cell library engineer
Builds
Custom standard cell collateral (circuit, layout, models) for Intel Foundry
Domain
Semiconductor / Standard Cell Library Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Standard cell layout, Standard cell abstract modeling, Standard cell characterization, ASIC design and verification, Physical design flow implementation, Timing optimization, Power optimization, Signal integrity analysis, Reliability analysis, Data-driven experiment design
Preferred skills
Unix command line proficiency, Python scripting, Perl scripting
Technologies
Cadence Virtuoso, Synopsys Custom Compiler, Cadence Abstract Generator, Synopsys PrimeLib, Cadence Liberate, Synopsys Fusion Compiler, Cadence Innovus, Cadence Tempus, Synopsys PrimeTime, Synopsys HSpice, Synopsys StarRC, Synopsys ICV, Cadence Pegasus, Siemens Calibre
Responsibilities
Define, implement, characterize, and validate design solutions for PPA, manufacturability, and cost; Implement full physical design flow from circuit to layout and extraction; Collaborate with collateral teams to develop robust implementation strategies; Review and validate work for design, manufacturing, and quality compliance; Execute fast-turnaround experiments to guide data-driven decisions; Generate, validate, and release custom standard cell collateral on demand
Seniority
Senior, hands-on IC
