CareerPlan

Senior Circuit Design Engineer - Noise

US, CA, Santa ClaraFull-time$168k2026-08-26 → 2026-11-10
Hybrid

Core

Design innovative circuits (digital, semi-custom, mixed-signal analog) for silicon correlation and noise mitigation in deep submicron technologies.

Role type

Senior IC circuit design engineer (noise mitigation)

Builds

Next-generation NVIDIA processors and circuit IPs for voltage and noise sensing

Domain

Semiconductor / Deep submicron digital and mixed-signal analog design

Required skills

Transistor-level analysis, Spice simulations, EM/IR analysis, static timing analysis/closure, analog/mixed-signal block design (op-amp, comparator, ADC), deep submicron process knowledge, voltage sensor design, flash ADC design, RTL/logic synthesis, Place and Route, DFT, scripting (Perl, Tcl, Make)

Preferred skills

Leadership experience, automation methods/algorithms

Technologies

Spice, EM/IR, STA, Perl, Tcl, Make

Responsibilities

Design innovative circuits for silicon correlation and noise mitigation, perform detailed transistor-level analysis, drive design and physical implementation of circuit IPs, create prototypes of patentable ideas on test chips, mentor junior team members

Seniority

Senior, hands-on IC