Substrate IC Package Layout Design Engineer
Core
End-to-end design of complex IC substrate packages for high-power AI processors and accelerators, focusing on power delivery, high-speed signaling, and CoWoS integration.
Role type
Senior IC Package Layout Design Engineer
Builds
High-power, high-speed substrate packages and interposers for AI inference workloads
Domain
Semiconductor hardware / Advanced packaging / AI infrastructure
Deliverable
production ML models | product features
Required skills
IC substrate layout design, high-speed signal routing (>50GHz), power delivery network design, CoWoS interposer design, DRC/LVS verification, Allegro Package Designer, SI/PI principles
Preferred skills
Experience with large substrate designs (>50mm), experience with >700W custom silicon solutions, cross-functional co-design with silicon and OSAT providers
Technologies
Allegro Package Designer
Responsibilities
Lead design and development of complex multi-layer substrate packages with high pin counts; Develop high-speed signal routing solutions minimizing loss and crosstalk; Optimize CoWoS interposer designs for thermal and electrical performance; Perform DRC and LVS verification for all substrate designs; Develop and maintain design documentation and guidelines; Provide technical guidance to junior team members
Seniority
Senior, hands-on IC
