I/O Design Engineer
Core
Design and verification of analog and mixed-signal I/O IP, including CMOS I/O, bandgap references, op-amps, and comparators for advanced nodes.
Role type
Senior IC analog/mixed-signal I/O design engineer
Builds
Production I/O IP blocks and silicon bring-up for Broadcom's Central Engineering Group
Domain
Semiconductor IC design, analog/mixed-signal, advanced process nodes (FinFET/GAA)
Deliverable
production ML models | product features
Required skills
CMOS I/O design, high-precision analog circuit design (bandgap, op-amps, comparators), SPICE/Spectre simulation, Cadence Virtuoso, I/O protocols (GPIO, I2C, I3C, eMMC, RGMII, SPMI), transistor reliability analysis, EMIR analysis, Verilog modeling, IBIS modeling
Preferred skills
Experience with advanced CMOS FinFET and GAA process nodes, ESD/EMI/SI analysis, chip-level integration support
Technologies
Cadence Virtuoso, SPICE, Spectre, Verilog, Synopsys Liberty, IBIS
Responsibilities
Design CMOS I/O and analog circuits, run AC/DC performance and signal integrity simulations, perform reliability and EMIR analysis, collaborate with layout teams on physical design, build circuit models, create technical documentation, support silicon bring-up
Seniority
Senior, hands-on IC
