Analog IC Design

2,196 open positions

<Data center>Die-to-Die High Speed Analog Circuit and HBM/DDRPHY Design Engineer MediaTekHsinChu 6y Design of high-speed analog PHY circuits for chip-to-chip interfaces (UCIe, Die-to-Die) and memory interfaces (HBM, DDR, LPDDR).
Principal RF Photonics Engineer (d/m/f) ams-OSRAM AGPremstätten Driving lab metrology and PCB design methodology for electro-optical data transmission using Photonic Integrated Circuits (PICs).
Staff Engineer Technology Development (f/m/div) Infineon Technologies Austria AGVillach Design silicon power MOSFET masks and layouts, define design environments and rules, and develop electrical characterization structures for Ion Trap Systems.
VP Engineering, IC Design (On-site. West Lafayette, USA) IxanaWest Lafayette, IN Lead IC design teams to build brain-inspired wearable computing chips using patented Wi-R technology for real-time, AI-powered human-computer interaction.
Silicon Reverse Engineer SemiAnalysisHillsboro, OR Teardown and characterization of leading-edge AI and datacenter hardware (GPUs, CPUs, accelerators, memory, networking silicon) from rack to transistor to produce competitive insights and design analysis.
Staff Engineer – RF/Mixed Signal IC Design (On-site. Bengaluru, India) IxanaBengaluru, India Lead the design, tapeout, and validation of custom RF/mixed-signal silicon for next-generation brain-inspired wearables.
Analog/Mixed Signal IC Design Engineer (On-site. Bengaluru, India) IxanaBengaluru, India Design and analyze mixed-signal and RF circuits for low-power wireless communication in wearable computing chips.
模拟芯片设计工程师（芯片平台） - 芯片研发 ByteDance深圳 Design and deliver analog IP blocks including high-speed interfaces, ADC/DAC, DC/DC, LDO, Amplifiers, Reference Generators, and monitoring circuits for a unified chip design platform.
MR显示屏驱动专家（OLED背板/DDIC方向） - PICO ByteDance上海 Expert in OLED/Micro-OLED backplane and DDIC design, managing supplier technical alignment, design review, and mass production readiness for high-PPI micro-displays.
Analog and Mixed Signal Design Engineer -Singapore TikTokSingapore Lead analog design of complex IPs for SoC in high-performance, energy-efficient CPUs for data center servers.
连接器/Cable工程师-Data ByteDance深圳 Full lifecycle R&D design of custom connectors (high-speed/power) and cables, including performance testing, supplier management, and technical problem resolution.
热设计工程师-服务器研发 ByteDance深圳 Design and simulate thermal solutions for server chips, packages, and board-level EVBs, focusing on TTV design, power/performance analysis, and heat source layout.
图像传感器模拟设计专家-PICO ByteDance上海 Design pixel and readout circuits for AR/VR image sensors and lead peripheral IP development.
About the job SK GroupKorea Develop and validate Ruledecks for DRC/LVS/LPE using Siemens/Synopsys/Cadence tools; build verification environments and automation utilities.
Director – IC Design (On-site. Bengaluru, India) IxanaBengaluru, India Lead the vision, design, and delivery of cutting-edge silicon and high-performance mixed-signal/analog circuits for brain-inspired wearable computing products.
版图设计工程师（西安） - 芯片研发 ByteDance西安 Layout design engineer for custom hardware optimization in cloud chips, collaborating with circuit designers to create reliable layouts for advanced semiconductor processes.
Berufseinstieg für HTL-Absolventen: Analog Layout Engineer (w/m/div)* Infineon Technologies Austria AGVillach €41k Develop analog chip layouts for microchips used in automotive, power management, and industrial applications.
Senior Staff Engineer Module Simulation and Methodology (f/m/div) Infineon Technologies Austria AGVillach Develop and optimize simulation methodologies for semiconductor devices, circuits, and Intermediate Bus Converters, correlating results with hardware data to support failure analysis.
Staff Engineer Analog Design (f/m/div) Infineon Technologies Austria AGVillach Design and develop analog and mixed-signal circuit blocks from concept to silicon validation for highly integrated semiconductor solutions enabling efficient power conversion and intelligent energy management.
Senior Staff Concept Engineer Technology Development for E-mobility (f/m/div) Infineon Technologies Austria AGVillach Define technical directions and drive innovation for next-generation automotive power SiC MOSFET technologies, focusing on device architecture and technology concepts.
Staff Engineer Analog Design (f/m/div) Infineon Technologies Austria AGVillach Design and develop analog and mixed-signal circuit blocks from concept to silicon validation for highly integrated semiconductor solutions enabling efficient power conversion and intelligent energy management.
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System Solution Engineer - Optical Interconnect CMOS ICs for Datacom (d/m/f) Premstätten Define future optical connectivity for AI and data centers by translating customer architectures into differentiated IC product concepts and roadmaps.
Staff Engineer – RF/Mixed Signal IC Design (On-site. West Lafayette, USA) IxanaWest Lafayette, IN $160k Lead the end-to-end design, verification, and integration of analog and mixed-signal IPs into Wi-R System-on-Chips (SoCs), focusing on RF IC development from architecture to post-silicon bring-up.
Senior IC/MEMS Integration and Simulation Engineer Odd / TFLHybrid Design microbolometer MEMS architecture and electrical/mechanical interfaces with ROIC for thermal imaging sensors.
高级光互连工程师（相干方向） TencentShenzhen, China Define technical roadmaps for coherent optical interconnects in DCI and metro scenarios, specifying modulation formats, FEC schemes, and rate selections to balance cost, power, and performance.
Internship - Lab Verification Engineer in the AMS Lab of the Development Center Villach (f/m/div) Infineon Technologies Austria AGVillach Internship role supporting the Analog-Mixed-Signal (AMS) verification laboratory at Infineon's Development Center Villach, focusing on verifying analog and digital measurement devices.
IC Layout Engineer SemiAnalysisHillsboro, OR Analyze the physical design, layout, and manufacturing implementation of leading-edge integrated circuits (AI/datacenter hardware) to derive architectural and competitive insights.
芯片模拟/混合信号设计工程师-Data（深圳） ByteDance深圳 Design complex SOC analog circuit IPs and define architecture solutions for product adaptation.
ADDA/模拟信号链设计工程师（存算与AI） - 芯片研发 ByteDance北京 Design high-efficiency AI chips using in-memory computing architectures to overcome the 'memory wall' bottleneck, focusing on ADC/DAC and analog signal chain IP for AI large model applications.
版图设计工程师（深圳） - 芯片研发 ByteDance深圳 Designing layout for custom hardware blocks to optimize performance and reduce costs for ByteDance's business scenarios.
版图设计工程师（芯片平台） - 芯片研发 ByteDance西安 Designing physical layouts for chip blocks within a unified platform covering logic synthesis to mass production, supporting multi-process and multi-project automated flows.
模拟开发工程师（电源方向/存算与AI） - 芯片研发 ByteDance北京 Designing high-efficiency AI chips based on in-memory computing architecture to break the 'memory wall' bottleneck and provide a high-efficiency computing base for AI business scenarios.
Staff Engineer Mixed Signal Layout (f/m/div.) Infineon Technologies Austria AGVillach Execute full-custom IC and block-level layout from schematic to tape-out for high-frequency RF blocks and high-speed SerDes components.
芯片封装设计/SIPI（芯片平台） - 芯片研发 ByteDance北京 Provide chip packaging design solutions including package selection, design, implementation, PinMap definition, and board-level interconnect; analyze and optimize signal integrity (SI) and power integrity (PI) for complex SoCs with high-speed interfaces.
封装设计工程师（存算与AI） - 芯片研发 ByteDance深圳 Lead high-bandwidth memory packaging design and optimization for AI chips, focusing on TSV, Microbump, and Interposer designs to enable high-efficiency computing.
存算设计工程师（存算与AI） - 芯片研发 ByteDance北京 Design high-efficiency AI chips based on in-memory computing architecture to break the 'memory wall' bottleneck and serve AI large model applications.
信号/电源完整性（SI/PI）工程师-Data ByteDance杭州 System-level SI/PI scheme design and simulation for server platforms, including board-level high-speed component selection, PCB stack-up optimization, and chip power integrity strategies.
Staff Analogue Designer, CMOS Modelling IonQOxford / England $30k–$90k Own full-chip mixed-signal CMOS modelling and behavioural model development for cryo-CMOS ASICS controlling quantum processors.
3DIC系统仿真工程师（存算与AI） - 芯片研发 ByteDance深圳 3DIC chip Signal Integrity (SI) and Power Integrity (PI) sign-off and full-system simulation for AI chips.
光通信SerDes链路研发专家 ByteDance杭州 Designing and simulating SerDes link architectures for optical communication systems to ensure high-speed data transmission performance and stability.
工艺&可靠性工程师-服务器研发 ByteDance深圳 Develop board-level process solutions and reliability designs for server and chip projects, including DFM/DFR, packaging engineering, and new material/process validation.
PCB专家/工程师-创新业务 ByteDance深圳 Design and implement PCB board-level interconnect solutions for mobile and wearable products, ensuring reliability, compatibility, and manufactability across high-speed, power, and multi-board scenarios.
模拟IP K库工程师（芯片平台） - 芯片研发 ByteDance北京 Deliver timing and power libraries (CCS/LVF/CMM/APL/Verilog) for analog/mixed-signal IPs including PLLs, LDOs, power switches, decaps, and high-speed interfaces (SerDes/UCIe) across the chip design flow.
图像传感器模拟设计专家-PICO ByteDance北京 Design pixel and readout circuits for custom image sensors in AR/VR products, leading peripheral IP development and chip-level integration.
芯片模拟/混合信号设计工程师-Data（上海） ByteDance上海 Lead design of complex SOC analog circuit IPs and define optimal architectures for products in advanced process nodes.
Staff Packaging Engineer AdeiaSan Jose $170k–$205k Develop and optimize semiconductor packaging solutions from silicon die through PCB-level integration, supporting advanced packaging development, structural/thermal analysis, and manufacturing readiness.

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