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Hardware & Physical Engineering
› Analog IC Design
Analog IC Design
1,385 open positions
Sr Layout Engineer
Monolithicpower
Barcelona, Spain
5mo
Lead IC layout activities from floorplanning through tape-out for integrated power semiconductors.
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Senior Manager IP Design
Micron
Hyderabad, Telangana, India
5mo
Leading an IP circuit design group in India to develop critical analog and digital IP circuits for DRAM memory products.
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Senior Manager IP Design
Micron
Hyderabad - Phoenix Aquila, India
5mo
Leading a design team in India to develop critical IP circuits for all DRAM-related memory products.
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Analog Engineer Intern - PhD
Marvell
Ottawa, Canada
$75k–$100k
5mo
Design and validation of FET and BiCMOS circuits for high-speed broadband ICs serving data center, metro, and long-haul fiber optic communication applications.
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IO/ESD Layout Engineer (Senior/Staff)
MediaTek
Singapore
5mo
Physical implementation of custom integrated circuitries including IO/ESD, Standard Cells, Memory Compilers, Analog IP, and RF building blocks for advanced semiconductor technology.
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ENGR PRIN, PRODUCT; PROD&TEST
ON Semiconductor
Bangalore, Karnataka, India
5mo
Designing and qualifying ATE (Automatic Test Equipment) hardware, including probe-cards, loadboards, and mechanical interfaces for semiconductor testing in automotive and industrial markets.
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Analog IC Design Manager m/f/d
Texas Instruments
Freising, Bayern, Germany
5mo
Lead mixed-signal IC design and layout teams to bring precision ICs integrating high-resolution ADCs, DACs, amplifiers, references, data communication, and power management to market.
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Senior Circuit Design Engineer - Power Delivery
NVIDIA
US, CA, Santa Clara
$168k–$168k
5mo
Designing analog/mixed-signal circuits and voltage regulation solutions for power delivery in deep submicron technologies.
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RF Technology Development Device Engineer - MTS
GlobalFoundries
Essex Junction
$98k–$98k
5mo
Develop and optimize SiGe HBTs and RF CMOS devices using TCAD simulation, electrical characterization, and process integration for RF technology.
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CPU circuit robustness management engineer
MediaTek
HsinChu
5mo
Review CPU IP pre-silicon circuit design weaknesses and develop post-silicon test items to screen circuit weaknesses.
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ENGR SR, PRODUCT; PROD & TEST
ON Semiconductor
Bangalore, Karnataka, India
5mo
Drive development, validation, and mass production of mixed-signal image sensors from definition to market release.
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LPDDR Layout Design Engineer
Micron
Hashimoto, Japan
5mo
Designing and analyzing digital and analog circuits for memory products, overseeing layout processes including floor-planning, placement, and routing.
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Staff Engineer - Analog Layout
Micron
Bengaluru, India
5mo
Lead full-custom layout for complex Analog / Mixed-Signal IP blocks including bandgap references, LDOs, charge pumps, PLLs, and temperature sensors, ensuring quality from floor-planning to tape-out.
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Sr. Staff Analog Engineer
Semtech
IND - Hyderabad
5mo
Designing and optimizing analog CMOS integrated circuits and mixed-signal systems from specification to production.
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MTS Packaging Integration Engineer
GlobalFoundries
USA - Vermont - Essex Junction
$94k–$94k
5mo
Deliver industry-leading electro-optical transceivers using GF's Photonix platform and advanced 2.5D/3D co-packaged optics form factors, focusing on tool-process interactions for SiPh Flip Chip assembly and module reliability.
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Engineer, HIG-HBM Product & System Engineering (Media Health Manufacturing)
Micron
Fab 10A, Singapore
5mo
Drive manufacturing test flow development, validation, and yield improvement for next-generation High Bandwidth Memory (HBM) products including DRAM, interface, and stacked die.
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Sr Analog Engineer
Renesas-Electronics
Seongnam-si, Gyeonggi-do, kr
5mo
Design and industrialize highly configurable mixed-signal products (GreenPAK family) for consumer, communication, computing, data center, industrial, and automotive applications.
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Package Architect – Advanced Packaging & System Exploration
Micron
Boise, ID - Main Site, US
$177k–$177k
5mo
Define and explore advanced package architectures for future memory systems, performing trade-off studies and creating hands-on designs for early feasibility analysis.
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Analog IC Design Engineer | INT TRX
Texas Instruments
Dallas, TX, United States
5mo
Designing, developing, and modifying analog and mixed-signal integrated circuits from concept through tape-out and mass production.
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Substrate/Package Layout Engineer
Broadcom
USA-California-San Jose-1320 Ridder Park Drive
$141k–$141k
5mo
Design and layout advanced substrates and IC packages, including high-speed lines and interposers, ensuring functionality and performance.
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ESD Lead
Texas Instruments
India
5mo
Design, develop, and implement ESD protection structures for analog products to improve design quality and eliminate ESD-induced failures.
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Signal Integrity Architect – System & IO Architecture
Micron
Boise, ID - Main Site, US
$177k–$177k
5mo
Define SI architectural strategies for high-speed memory and system interfaces, performing early feasibility and scaling analysis for future data rates.
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Sr. RF IC Design Engineer
MediaTek
Cambourne
5mo
Designing and verifying complete sub-systems for 6G cellular RF ICs, focusing on innovative signal path or synthesizer designs with leading edge performance.
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NAND PI Design Rule Snr Engineer
Micron
Fab 10N/X, Singapore
5mo
Define physical design rules for Non-Volatile Memory (NVM) technologies from conception to production, ensuring accuracy for layout and mask generation.
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DRAM Systems Architecture
Micron
Boise, ID - Main Site, US
$177k–$177k
5mo
Define next-generation memory system architectures focusing on performance, capacity, reliability, and telemetry while leading cross-stack co-optimization from silicon to system level.
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Staff HBM Design Architect
Micron
Richardson, TX, US
$146k–$146k
5mo
Design and analyze digital and analog DRAM circuits for advanced HBM products to enable breakthrough technologies in AI, ML, and high-performance computing.
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Analog IC Design Engineering Intern m/f/d
Texas Instruments
Freising, Bayern, Germany
5mo
Architect new TI products by defining, designing, modeling, implementing, and documenting analog circuits across domains like automotive, storage, and power supply.
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DMTS, Systems Architect
Micron
San Jose, CA, US
$208k–$208k
5mo
Define and evolve DRAM system architectures addressing performance, capacity scaling, reliability, and observability for next-generation memory products.
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ASIC Analog Layout Engineer (m/f/d) - REF5390S
Frankfurt am Main, HESSEN
5mo
Top-level integration of analog and mixed-signal ICs, driving layout development for robust, DRC-compliant designs with optimal area utilization.
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Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)
Micron
Hyderabad - Phoenix Aquila, India
5mo
Senior IC physical design engineer executing advanced packaging design strategy for High Bandwidth Memory (HBM) product integration.
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Principal Engineer Advanced Package Technology Development
Micron
Fab 10N/X, Singapore
5mo
Lead the development of advanced semiconductor packaging technologies, including 2.5D and 3D integration strategies, to drive innovation and strategic goals for memory solutions.
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RF/Analog Mixed Signal Design Engineer
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Apple
Sunnyvale, CA, US
$129k–$129k
5mo
Design transistor-level custom analog and mixed-signal ICs for Apple Silicon to connect products to the physical world and optimize performance.
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Principal Engineer , ASIC Analog Design
Micron
Bengaluru, India
5mo
Designing and implementing high-speed analog sub-blocks (PLL, DLL, CDR, equalization) for next-generation memory and storage interfaces in deep sub-micron technologies.
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ENGR STAFF, PRODUCT; PROD&TEST
ON Semiconductor
Bangalore, Karnataka, India
5mo
Drive development, validation, and mass production of mixed signal image sensors within the Intelligent sensing group.
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3DIC Advance Package Design Engineer
MediaTek
HsinChu
5mo
Developing and enhancing design methodologies, flows, and interposer designs for 2.5D and 3D IC advanced packages.
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ASIC Link Modeling Technical Leader
Cisco
Carlsbad, California, US
$189k–$189k
5mo
Develop system-level behavioral models and comprehensive link simulations for Cisco's silicon photonics systems, enabling performance analysis across high-speed SerDes, optical DSP, and die-to-die interfaces for next-generation 100G/200G/400G per Lambda…
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Advanced CMOS Device & Process Integration Engineer
Micron
Hiroshima - Fab 15, Japan
5mo
Developing and integrating advanced CMOS devices (FinFET, Nano-sheets, vertical GAA) for high-volume manufacturing in memory and storage solutions.
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Staff Design Engineer
Micron
Tokyo, Japan
5mo
Designing, simulating, optimizing, and floor planning NAND circuits while building Python-based AI utilities to accelerate design tasks.
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Sr. ASIC Layout Design Engineer
Flir
US - Goleta, CA
$114k–$114k
5mo
Develop high-performance focal-plane array readout integrated circuits (ROICs) for infrared detectors, sensors, and cameras used in aerospace, defense, and scientific research.
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Principle Product and Test Engineer
ON Semiconductor
Allen, TX, United States
5mo
Design and productize automated test solutions for Analog, Mixed Signal, and Digital ICs to support new product development and execution in Automotive and Industrial markets.
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Semiconductor Principal Design Engineer, Non‑Volatile Engineering Group
Micron
Tokyo, Japan
5mo
Own and evolve timing-critical circuitry between the NAND array and page buffer, driving designs that impact throughput, timing margin, power, and yield.
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R&D Engineering, Principal Engineer
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Synopsys
Markham, ON, CA
5mo
Principal Engineer leading high-speed analog and mixed-signal layout methodologies for advanced SerDes IP.
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R&D Engineer Hardware 5
Broadcom
USA-CA San Jose Innovation Drive
$141k–$141k
5mo
Design, develop, and deliver Ultra High-performance electronic products with full lifecycle ownership from conception to sustained high volume production.
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Global Commodity Manager – Photonics Components
Ciena
Ottawa
$97k–$97k
5mo
Lead global commodity strategy and supplier ecosystem development for optical active photonic components to ensure cost-competitive, long-term supply assurance.
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Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer
Arista-Networks
Santa Clara, CA, us
$150k–$230k
5mo
Lead the design, simulation, and validation of high-speed electrical interconnects and power delivery networks (PDNs) for next-generation optical modules and engines.
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Principal Signal Power Integrity Engineer, Texas Institute for Electronics
Utaustin
AUSTIN, TX
5mo
Lead end-to-end Signal Integrity (SI) and Power Integrity (PI) simulations for advanced 2.5D/3.0D heterogeneous integration packages and multi-chiplet stacks.
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Field Application Engineer - FPGA Prototyping
Siemens-Eda
Los Angeles, CA, United States
$147k–$293k
5mo
Senior technical contributor driving business growth through strategic customer engagement, leading technical sales campaigns, and ensuring customer success for EDA solutions.
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R&D Engineer Adv Tech Dev (PKE) / Sr. Staff
Broadcom
Singapore-Yishun
5mo
Lead IC packaging engineering for advanced silicon nodes (5nm, 3nm, 2nm), defining custom package solutions, materials, and processes to meet signal integrity, power integrity, and thermal requirements.
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MTS - ESD Design Engineer
Micron
Bengaluru, India
5mo
Lead ESD architecture and protection strategy for high-speed I/O portfolios including HBM, DDR, and proprietary interfaces to ensure silicon success without compromising performance.
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Design Methodology – Principal DRAM Power Integrity Engineer
Micron
Hyderabad - Phoenix Aquila, India
5mo
Develop and standardize EMIR methodology and perform static/dynamic EM/IR and PDN analysis for advanced DRAM products.
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