Lead Analog Layout Design Engineer (SerDes)
Core
Lead Technical Designer for high-speed SERDES analog/mixed-signal layouts in UCIe products.
Role type
Lead Analog Layout Design Engineer (SerDes)
Builds
Custom layout designs for high-speed SERDES IP blocks and PHY top-level integration.
Domain
Semiconductor IC Design / High-Speed SerDes / UCIe
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
High-speed SERDES layout design, Analog/mixed-signal circuit layout, Floor planning, Foundry design rule verification, Block-level to PHY-level integration, Driver/Receiver/Serializer/Deserializer design, Phase Interpolator design, Low jitter PLL design, High-speed clock distribution, Bias and Bandgap design, Voltage Regulator design
Preferred skills
Cadence Virtuoso tool experience, PVS verification tool development, Sub-16nm technology node experience, >10Gbps design experience
Responsibilities
Design high-speed SERDES layouts up to 64 Gbps on leading-edge nodes, Execute back-end flow from floor planning to final verification, Lead technical aspects of layout design from block to PHY integration, Collaborate with global circuit designers and project managers, Work with global teams across different time zones
Seniority
Senior, hands-on IC design with technical leadership